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Phase 1 — Rust Resource Manager + cxx Bridge

Status: complete (2026-05-24). MVP issues #13–#20 closed; KPU pieces #21–#23 deferred behind the phase-soc-deferred label.

Phase 1 delivered a SITL-only Rust Resource Manager exposing a strictly typed memory-allocation surface to C++ via the cxx bridge, plus a lifecycle state machine.

  1. Call into Rust to request a zero-copy buffer of arbitrary size and alignment.
  2. Lock the buffer to obtain a raw pointer + TensorMetadata, write into it, and have the bytes be visible from the Rust side after release.
  3. Walk an operator through Unconfigured → Inactive → Active → Teardown, with invalid transitions returning typed errors — never a panic.
  • MemoryProvider trait — the object-safe allocate/release/lock surface. SitlMemoryProvider (POSIX shm + mmap, heap fallback) and KpuMemoryProvider (a stub returning Err(NotYetImplemented)). Both compile in; the active one is chosen at construction from RUST_HAL_TARGET.
  • BufferHandle — an opaque #[repr(transparent)] u64 with a private inner field, so external callers can’t fabricate handles.
  • The cxx bridgecore/src/lib.rs, #[cxx::bridge(namespace = "branes::core")], headers generated by build.rs; TensorMetadata crosses repr(C) as pointer + shape, wrapped in std::span on the C++ side without copying.
  • Lifecycle state machine — the managed configure/activate/teardown flow that the C++ VioEstimator later mirrors.

See Resource Manager for the architectural detail.

The Rust core is gated at ≥85% line coverage (cargo-llvm-cov) and verified by a C++/Rust integration test exercising the bridge end-to-end. This phase unblocked the math (Phase 2) and VIO (Phase 3) work above it.

The IPC broker over UDS + POSIX shm (#21), crash-only recovery / client replay (#22), and the KPU resource-allocation arbiter (#23) are parked until the silicon path is active.

Companion: docs/arch/phase1-design/README.md, docs/sessions/2026-05-24-phase-1-mvp-complete.md.